1. Field of the Invention
An aspect of this disclosure relates to a successive approximation AD converter and a successive approximation AD conversion method.
2. Description of the Related Art
A microprocessor is generally provided in a portable electronic apparatus such as a cell phone, a personal digital assistant (PDA), or a digital camera to control a system in the electronic apparatus. For example, the microprocessor monitors and controls the temperature of the electronic apparatus and the voltage of a battery in the electronic apparatus. For this purpose, an electronic apparatus generally includes sensors for detecting its temperature and a battery voltage, and a microprocessor of the electronic apparatus typically includes an analog-to-digital (AD) converter for converting analog signals output from the sensors into digital signals. An AD converter to be included in a microprocessor preferably has a small circuit size. An example of such an AD converter is a successive approximation AD converter.
FIG. 18 is a circuit diagram illustrating a configuration of a related-art successive approximation AD converter. In FIG. 18, an analog voltage Vin is input to an input terminal 10. A sample-and-hold circuit 11 samples and holds a voltage difference between the analog voltage Vin and an output voltage of a digital-to-analog (DA) converter 14 with reference to a reference voltage Vref.
A dynamic latch comparator 12 compares an output voltage of the sample-and-hold circuit 11 with the reference voltage Vref and supplies the comparison result, which indicates whether the analog voltage Vin is greater or less than the output voltage of the DA converter 14, to a successive approximation register and operation unit 13. The successive approximation register and operation unit 13 generates next (or subsequent) DA conversion data (data to be converted in the next DA conversion process) based on the comparison result supplied from the dynamic latch comparator 12, and supplies the generated data to the DA converter 14. The successive approximation register and operation unit 13 also supplies digital data, which is a final conversion result, to an output circuit 16.
A control circuit 15 receives a clock signal and a conversion start command, generates timing signals φ1, φ2, and φ3, supplies the timing signals φ1, φ2, and φ3 to the sample-and-hold circuit 11 and the dynamic latch comparator 12, generates a control signal indicating a start or an end, and supplies the control signal to the successive approximation register and operation unit 13. The output circuit 16 outputs the digital data that is the final conversion result.
First, the timing signal φ1 is set at 1 and the timing signal φ2 is set at 0 to turn on switches SW1 and SW3 and turn off a switch SW2 of the sample-and-hold circuit 11. As a result, a charge corresponding to (Vref−Vin) is stored in a capacitor C1 of the sample-and-hold circuit 11.
Next, a DAC voltage VDAC is output from the DA converter 14, and the timing signal φ1 is set at 0 and the timing signal φ2 is set at 1 to turn off the switches SW1 and SW3 and turn on the switch SW2 of the sample-and-hold circuit 11. As a result, a voltage VA at a terminal of the capacitor C1 on the side of a differential amplifier 11a becomes VA=Vref+(VDAC−Vin). The voltage VA indicates a voltage difference between the DAC voltage VDAC and the input voltage Vin with reference to the reference voltage Vref. The successive approximation register and operation unit 13 generates next DA conversion data based on the comparison result supplied from the dynamic latch comparator 12. The above-described successive approximation process is repeated from the most significant bit (MSB) to the least significant bit (LSB) of DA conversion data (data to be converted from analog to digital) to generate digital data that is the final conversion result.
Japanese Laid-Open Patent Publication No. 2010-245927 discloses a successive approximation AD conversion circuit including a comparison circuit for comparing an input analog voltage and a comparison voltage. The comparison circuit includes an initial amplifier stage that is used in common, a first comparison unit including a first amplifier stage connected via a coupling capacitor to the initial amplifier stage, a second comparison unit including a second amplifier stage connected via a coupling capacitor to the initial amplifier stage, a first comparison point shift circuit connected to an input terminal of the first amplifier stage, and a second comparison point shift circuit connected to an input terminal of the second amplifier stage. The first comparison point shift circuit and the second comparison point shift circuit shift the comparison voltage for a predetermined amount in opposite directions when amplifying a potential difference between the input analog voltage and the comparison voltage.
Japanese Laid-Open Patent Publication No. 2011-120011 discloses an analog-digital converter including a DAC that outputs a reference analog signal corresponding to a multi-bit digital signal, first and second comparators that compare an input analog signal Vin with the reference analog signal, a selection circuit that selects one of the comparison results of the first and second comparators, and a control circuit that sequentially changes the multi-bit digital signal in multiple steps based on the selected comparison result such that the reference analog signal becomes close to the input analog signal. The control circuit controls the selection circuit to select the comparison result of the first comparator in steps up to a middle step and select the comparison result of the second comparator in steps following the middle step, and thereby changes bit values of the multi-bit digital signal according to a non-binary algorithm.
With the related-art configuration of FIG. 18, however, the successive approximation AD converter requires a long settling time that is the time from when the DA converter 14 starts outputting the DAC voltage VDAC until when the voltage VA of the terminal of the capacitor C1 on the side of the differential amplifier 11a becomes stable at VA=Vref+(VDAC−Vin) and the dynamic latch comparator 12 becomes able to output correct comparison results. Accordingly, the related-art successive approximation AD converter requires a long conversion time.
Also, the successive approximation AD conversion circuit of Japanese Laid-Open Patent Publication No. 2010-245927 requires two comparison units, i.e., the first comparison unit and the second comparison unit. With this configuration, it is troublesome to adjust the two comparison units to make their comparison characteristics the same.